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  i 2 c ? cmos 8 12 unbuffered analog switch array with dual/single supplies d ata sheet adg2128 rev. d document feedback information furnished by analog devices is believed to b e accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.47 00 ? 2006 C 2012 analog devices, inc. all rights reserved. technical support www.analog.com f eatures i 2 c- compatible i nterface 3.4 mhz high speed i 2 c option 32 -l ead lfcsp _vq (5 mm 5 mm) double - buffered input l ogic simultaneous update of multiple switches up to 300 mhz bandwidth fully specified at d ual 5 v/s ingle + 12 v o peration on r esistance 3 5 ? max imum low quiescent c urrent < 20 a qualified for automotive applications a pplications av s witching in tv automotive i nfotainment av receivers cctv ultrasound applications kvm switching telecom applications test equipment/instrumentation pbx systems g eneral description the adg2128 is an analog cross point switch with an array size of 8 12. the switch array is arranged so that t here are eight columns by 12 rows, for a total of 96 switch channels. the array is bidirectional, and the rows and columns can be configured as either inputs or outputs. each of the 96 switches can be addressed and configured through the i 2 c- compatible interface. standard, full speed, and high speed (3.4 mhz) i 2 c interfaces are supported. any simultaneous switch combination is allowed . an additional feature of the adg2128 is that switches can be updated simultaneously, using the ldsw command. in addition, a reset option allows all of the switch cha nnels to be reset/off. at power - on, all switches are in the off condition. the device is packaged in a 32 - lead, 5 mm 5 mm lfcsp_vq. f unctional block diag ram adg2128 v dd v ss v l scl sda x0 to x11 (i/o) 8 12 switch array ldsw 96 1 96 1 input register and 7 to 96 decoder latches ldsw gnd a0a1a2 y0 to y7 (i/o) 05464-001 figure 1.
adg2128 data sheet rev. d | page 2 of 28 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 functional block diagram .............................................................. 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 i 2 c timing specifications ............................................................ 7 timing diagram ........................................................................... 8 absolute maximum ratings ............................................................ 9 esd caution .................................................................................. 9 pin configuration and function descriptions ........................... 10 typical performance characteristics ........................................... 11 te st c irc ui ts ..................................................................................... 15 terminology .................................................................................... 17 theory of operation ...................................................................... 18 reset /power - on reset ............................................................ 18 load switch (ldsw) ................................................................. 18 readback ..................................................................................... 18 serial i nterface ................................................................................ 19 high speed i 2 c interface ........................................................... 19 serial bus address ...................................................................... 19 wr iting to the adg2128 ............................................................... 20 input shift register .................................................................... 20 write operation .......................................................................... 22 read operation ........................................................................... 22 evaluation board ............................................................................ 24 using the adg2128 evaluation board ................................... 24 power supply ............................................................................... 24 schematics ................................................................................... 25 outline dimensions ....................................................................... 27 ordering guide .......................................................................... 27 automotive products ................................................................. 27 revision history 10 /12 rev. c to rev. d changes to ordering guide .......................................................... 27 8/12 rev. b to rev. c updated outline dimensi ons (changed cp -32- 1 to cp -32- 7) ...... 27 changes to ordering guide .......................................................... 27 11/11 rev. a to rev. b changes to fea t ures section ........................................................... 1 changes to schematics section .................................................... 25 updated outline dimensions ....................................................... 27 changes to the ordering guide .................................................... 27 added automotive products section ........................................... 27 5 /0 6 rev. 0 to rev. a added i 2 c information ...................................................... universal changes to table 1 ............................................................................. 3 changes to table 2 ............................................................................. 5 changes to table 4 ............................................................................. 9 changes to figure 24 ...................................................................... 14 changes to terminology section ................................................. 17 changes to figure 35 ...................................................................... 23 changes to the ordering guide ................................................... 27 1 /06 revision 0: initial ve rsion
data sheet adg2128 rev. d | page 3 of 28 specifications v dd = 12 v 10% , v ss = 0 v, v l = 5 v, gnd = 0 v, all specifications t min to t max, unless otherwise noted. 1 table 1. parameter b version y version unit conditions +25c ?40c to +85c +25c ?40c to +125c analog switch analog signal range v dd ? 2 v v dd ? 2 v v max on resistance, r on 30 30 ? typ v dd = + 10.8 v, v in = 0 v, i s = ?10 ma 35 40 35 42 ? max 32 32 ? typ v dd = + 10.8 v, v in = + 1.4 v, i s = ?10 ma 37 42 37 47 ? max 45 45 ? typ v dd = + 10.8 v, v in = + 5.4 v, i s = ?10 ma 50 57 50 62 ? max on resistance matching 4.5 4.5 ? typ v dd = + 10.8 v, v in = 0 v, i s = ?10 ma between channels, ?r on 8 9 8 10 ? max on resistance flatness, r flat(on) 2.3 2.3 ? typ v dd = 10.8 v, v in = 0 v to + 1.4 v, i s = ?10 ma 3.5 4 3.5 5 ? max 14.5 14.5 ? typ v dd = 10.8 v, v in = 0 v to + 5.4 v, i s = ?10 ma 18 20 18 22 ? max leakage currents v dd = 13.2 v channel off leakage, i off 0.03 0.03 a typ v x = 7 v/1 v, v y = 1 v/7 v channel on leakage, i on 0.03 0.03 a typ v x = v y = 1 v or 7 v dynamic characteristics 2 c off 11 11 pf typ c on 18.5 18.5 pf typ t on 170 170 ns typ r l = 300 ?, c l = 35 pf 185 190 185 195 ns max t off 210 210 ns typ r l = 300 ?, c l = 35 pf 250 255 250 260 ns max thd + n 0.04 0.04 % typ r l = 10 k ? , f = 20 hz to 20 khz, v s = 1 v p -p psrr 90 db typ f = 20 khz; without decoupling; see figure 24 ?3 db bandwidth 2 10 210 mhz typ individual inputs to outputs 16.5 16.5 mhz typ 8 inputs to 1 output off isolation ?69 ?69 db typ r l = 75 ?, c l = 5 pf, f = 5 mhz channel - to - channel crosstalk r l = 75 ?, c l = 5 pf, f = 5 mhz adjacent c hannels ?63 ?63 db ty p nonad jacent c hannels ?76 ?76 db typ differential gain 0.4 0.4 % typ r l = 75 ?, c l = 5 pf, f = 5 mhz differential phase 0.6 0.6 typ r l = 75 ?, c l = 5 pf, f = 5 mhz charge injection ?3.5 ?3.5 pc typ v s = 4 v, r s = 0 ?, c l = 1 nf logic inputs (ax, reset ) 2 input high voltage, v inh 2.0 2.0 v min input low voltage, v inl 0.8 0.8 v max input leakage current, i in 0.005 0.005 a typ 1 1 a max input capacitance, c in 7 7 pf typ
adg2128 data sheet rev. d | page 4 of 28 parameter b version y version unit conditions +25c ?40c to +85c +25c ?40c to +125c logic inputs (scl, sda) 2 input high voltage, v inh 0.7 v l 0.7 v l v min v l + 0.3 v l + 0.3 v max input low voltage, v inl ?0.3 ?0.3 v min 0.3 v l 0.3 v l v max input leakage current, i in 0.005 0.005 a typ v in = 0 v to v l 1 1 a max input hysteresis 0.05 v l 0.05 v l v min input capacitance, c in 7 7 pf typ logic output (sda) 2 output low voltage, v ol 0.4 0.4 v max i sink = 3 ma 0.6 0.6 v max i sink = 6 ma floating state leakage current 1 1 a max power requirements i dd 0.05 0.05 a typ digital i nputs = 0 v or v l 1 1 a max i ss 0.05 0 .05 a typ digital inputs = 0 v or v l 1 1 a max i l digital inputs = 0 v or v l interface i nactive 0.3 0.3 a typ 2 2 a max interface a ctive: 400 khz f scl 0.1 0.1 ma typ 0.2 0.2 ma max interface a ctive: 3.4 mhz f scl 0.4 0.4 ma typ - hs model only 1.2 1.7 ma max 1 temperature range is as follows: b version: ?40c to +85c; y version: ?40c to +125c. 2 guaranteed by design, not subject to production test.
data sheet adg2128 rev. d | page 5 of 28 v dd = +5 v 10% , v ss = ?5 v 10% , v l = 5 v, gnd = 0 v, all specifications t min to t max , unless otherwise noted. 1 table 2. b version y version parameter +25c ?40c to +125c +25c ?40c to +125c unit conditions analog switch analog signal range v dd ? 2 v v ma x on resistance, r on 34 34 ? typ v dd = +4.5 v, v ss = ?4.5 v, v in = v ss , i s = ?10 ma 40 45 40 50 ? max 50 50 ? typ v dd = +4.5 v, v ss = ?4.5 v, v in = 0 v, i s = ?10 ma 55 65 55 70 ? max 66 66 ? typ v dd = +4.5 v, v ss = ?4.5 v, v in = + 1.4 v, i s = ?10 ma 75 85 75 95 ? max on resistance matching 4.5 4.5 ? typ v dd = +4.5 v, v ss = ?4.5 v, v in = v ss , i s = ?10 ma between channels, ?r on 8 9 8 10 ? max on resistance flatness, r fl at (on) 17 17 ? typ v dd = +4.5 v, v ss = ?4.5 v, v in = v ss to 0 v, i s = ?10 ma 20 23 20 25 ? max 34 34 ? typ v dd = + 4.5 v, v ss = ?4.5 v, v in = v ss to + 1.4 v, i s = ?10 ma 42 45 42 48 ? max leakage currents v dd = 5. 5 v, v ss = 5.5 v channel off leakage, i off 0.03 0.03 a typ v x = +4.5 v/?2 v, v y = ?2 v/+4.5 v channel on leakage, i on 0.03 0.03 a typ v x = v y = ?2 v or +4.5 v dynamic characteristics 2 c off 6 6 pf typ c on 9.5 9.5 pf typ t on 170 170 ns typ r l = 300 ?, c l = 35 pf 200 215 200 220 ns max t off 210 210 ns typ r l = 300 ?, c l = 35 pf 250 255 250 260 ns max thd + n 0.04 0.04 % typ r l = 10 k ? , f = 20 hz to 20 khz, v s = 1 v p -p psrr 90 db typ f = 20 khz; without dec oupling; see figure 24 ?3 db bandwidth 300 300 mhz typ individual inputs to outputs 18 18 mhz typ 8 inputs to 1 output off isolation ?66 ?64 db typ r l = 75 ?, c l = 5 pf, f = 5 mhz channel - to - channel crosstalk r l = 75 ?, c l = 5 pf, f = 5 mhz adjacent c hannels ?62 ?62 db typ nonadjacent c hannels ?79 ?79 db typ differential gain 1.5 1.5 % typ r l = 75 ?, c l = 5 pf, f = 5 mhz differential phase 1.8 1.8 typ r l = 75 ?, c l = 5 pf, f = 5 mhz charge inje ction ?3 ?3 pc typ v s = 0 v, r s = 0 ?, c l = 1 nf logic inputs (ax, reset ) 2 input high voltage, v inh 2.0 2.0 v min input low voltage, v inl 0.8 0.8 v max input leakage current, i in 0.005 0.005 a typ 1 1 a max input capacitance, c in 7 7 pf typ logic inputs (scl, sda) 2 input high voltage, v inh 0.7 v l 0.7 v l v min v l + 0.3 v l + 0.3 v max input low voltage, v inl ?0.3 ?0.3 v min 0.3 v l 0.3 v l v max
adg2128 data sheet rev. d | page 6 of 28 b version y version parameter +25c ?40c to +125c +25c ?40c to +125c unit conditions input leakage current, i in 0.005 0.005 a typ v in = 0 v to v l 1 1 a max input hysteresis 0.05 v l 0.05 v l v min input capacitance, c in 7 7 pf typ logic output (sda) 2 output low voltage, v ol 0.4 0.4 v max i sink = 3 ma 0.6 0.6 v max i sink = 6 ma floating state leakage current 1 1 a max power requirements i dd 0.05 0.005 a typ digital inputs = 0 v or v l 1 1 a max i ss 0.05 0.005 a typ digital inputs = 0 v or v l 1 1 a max i l digital inputs = 0 v or v l interface i nactive 0.3 0.3 a typ 2 2 a max interface active: 400 khz f scl 0.1 0.1 ma typ 0.1 0.1 ma max interface active: 3.4 mhz f scl 0.4 0.4 ma typ - hs model only 0.3 0.3 ma max 1 temperature range is as follows: b version: C 40c to +85c; y version: C 40c to +125c. 2 guaranteed by desig n, not subject to production test.
data sheet adg2128 rev. d | page 7 of 28 i 2 c timing specificati ons v dd = 5 v to 12 v; v ss = ?5 v to 0 v; v l = 5 v; gnd = 0 v; t a = t min to t max , unless otherwise noted (see figure 2 ). table 3 . adg2108 limit at t min , t max parameter 1 conditions min max unit description f scl standard mode 100 khz serial clock frequency fast mode 400 khz high speed mode 2 c b = 100 pf maximum 3.4 mhz c b = 400 pf maximum 1.7 mh z t 1 standard mode 4 s t high , scl high time fast mode 0.6 s high speed mode 2 c b = 100 pf maximum 60 ns c b = 400 pf maximum 120 ns t 2 standard mode 4.7 s t low , scl low time fast mo de 1.3 s high speed mode 2 c b = 100 pf maximum 160 ns c b = 400 pf maximum 320 ns t 3 standard mode 250 ns t su;dat , data setup time fast mode 100 ns high speed mode 2 10 ns t 4 3 standard mode 0 3.45 s t hd; dat , data hold time fast mode 0 0.9 s high speed mode 2 c b = 100 pf maximum 0 70 ns c b = 400 pf maximum 0 150 ns t 5 standard mode 4.7 s t su;sta , setup time for a repeated start condition fast mode 0.6 s high speed mode 2 160 ns t 6 standard mode 4 s t hd;sta , hold ti me for a repeated start condition fast mode 0.6 s high speed m ode 2 160 ns t 7 standard mode 4.7 s t buf , bus free time betwe en a stop and a start condition fast mode 1.3 s t 8 standard mode 4 s t su;sto , setup time for a stop condition fast mode 0.6 s h igh speed mode 2 160 ns t 9 standard mode 1000 ns t rda , rise time of sda signal fast mode 20 + 0.1 c b 300 ns high speed mode 2 c b = 100 pf maximum 10 80 ns c b = 40 0 pf maximum 20 160 ns t 10 standard mode 300 ns t fda , fall time of sda signal fast mode 20 + 0.1 c b 300 ns high speed mode 2 c b = 100 pf maximum 10 80 ns c b = 400 pf maximum 20 160 ns
adg2128 data sheet rev. d | page 8 of 28 adg2108 limit at t min , t max parameter 1 conditions min max unit description t 11 standard mode 1000 ns t rcl , rise time of scl signal fast mode 20 + 0.1 c b 300 ns high speed mode 2 c b = 100 pf maximum 10 40 ns c b = 400 pf maximum 20 80 ns t 11a standard mode 1000 ns t rcl1 , rise time of scl signal after a repeated start fast mode 20 + 0.1 c b 300 ns condition and after an acknowledge bit high speed mode 2 c b = 100 pf maximum 10 80 ns c b = 400 pf maximum 20 160 ns t 12 standard mode 300 ns t fcl , fall time of scl signal fast mode 20 + 0.1 c b 300 ns high speed mode 2 c b = 100 pf maximum 10 40 ns c b = 400 pf maximum 20 80 ns t sp fast mode 0 50 ns pulse width of s uppressed spike high speed mode 2 0 10 ns 1 guaranteed by initial characterization. all values measured with input filtering enabled. c b refers to capacitive load on the bus line; t r and t f are measured between 0.3 v dd and 0.7 v dd . 2 high speed i 2 c is available only in - hs models. 3 a device must provide a data hold time for sda to bridge the undefined region of the scl falling edge. timing diagram p s s p sda scl s = start condition p = stop condition t 7 t 6 t 4 t 2 t 11 t 12 t 1 t 3 t 5 t 6 t 10 t 8 t 9 05464-002 figure 2 . timing diagram for 2 - wire serial interface
data sheet adg2128 rev. d | page 9 of 28 absolute maximum rat ings t a = 25c, unless otherwise noted . table 4. parameter rating v dd to v ss 15 v v dd to gnd ?0.3 v to +15 v v ss to gnd +0.3 v to ?7 v v l to gnd ?0.3 v to +7 v analog inputs v ss ? 0.3 v to v dd + 0.3 v digital inputs ?0.3 v to v l + 0.3 v or 30 ma, whichever occurs first continuous current 10 v on input; single input connected to single o utput 65 ma 1 v on input; single input connected to single o utput 90 ma 10 v on input; eight i nputs connected to eight o utput s 25 ma operating temperature range industrial (b version) C 40c to +85c automotive (y version) C 40c to +125c storage temperature range C 65c to +150c junction temperature 150c 32- lead lfcsp _vq ja thermal impedance 108.2c/w reflow soldering (pb free) peak temperature 260c (+0/ C 5) time at peak t emperature 10 sec to 40 sec stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a str ess rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect devic e reliability. esd caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although this product features propr ietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality.
adg2128 data sheet rev. d | page 10 of 28 pin configuration a nd function descriptions 05464-003 y2 y4 y3 y6 y7 y1 y0 y5 nc v dd x11 x10 x9 x8 x7 x6 x3 x1 x0 nc x5 x4 x2 v ss reset a1 scl a2 a0 sda gnd v l 1 2 3 4 5 6 7 8 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 9 10 11 13 14 15 16 12 pin 1 indic at or adg2128 12 8 top view (not to scale) notes 1. the exposed paddle is soldered to v ss . 2. nc = no connect. do not connect to this pin. figure 3 . pin configuration table 5 . pin function descriptions 1 pin no. mnemonic description 1 v ss negative p ower supply in a dual - supply a pplication. for single - supply appl ications, this pin should be tied to gnd. 2, 23 nc this pin is not connected internally (see figure 3 ). 3 to 8, 17 to 22 x0 to x11 can be inputs or outputs. 9 to 16 y0 to y7 can be inputs or outputs. 24 v dd positive power supply i nput. 25 v l l ogic power supply i nput. 26 sda digital i/o. bi directional open drain data line. external pull - up resistor required. 27 scl digital input, serial clock line. open drain input that is used in conjunction with sda to clock data into the device. external pull - up resistor required. 28 a0 logic input. address p in that sets the least significant bit of the 7 - bit slave address. 29 a1 logic input. address p in that sets the second least significant bit of the 7 - bit slave address. 30 a2 logic input. address p in that sets the third least significant bit of the 7 - bit slave address. 31 reset active low logic input. when this pin is low, all switches are open , and appropria te registers are cleared to 0 . 32 gnd ground reference point for all c ircuitry on the adg2128. epad exposed pad. the exposed paddle is soldered to v ss . 1 it is recommended that the exposed paddle be soldered to v ss to improve heat dissipation and crosstalk.
data sheet adg2128 rev. d | page 11 of 28 typical performance characteristics 200 0 ?5 12 source voltage (v) r on ( ?) 05464-007 180 160 140 120 100 80 60 40 20 ?4 ?3 ?2 ?1 0 1 2 3 4 5 6 7 8 9 10 11 v ss = ?5v v dd = +5v v ss = 0v v dd = +8v v ss = 0v v dd = +12v t a = 25c i ds = 10ma figure 4. signal range 85 75 65 55 45 35 25 ?5.5 1.5 0.5 ?0.5 ?1.5 ?2.5 ?3.5 ?4.5 source voltage (v) r on ( ?) 05464-017 v dd /v ss = 4.5v v dd /v ss = 5v v dd /v ss = 5.5v t a = 25c i ds = 10ma figure 5. r on vs. source voltage, dual 5 v supplies 70 65 60 55 50 45 40 35 30 25 20 0 87654321 source voltage (v) r on ( ?) 05464-018 v dd = 12v v dd = 10.8v v dd = 13.2v t a = 25c i ds = 10ma figure 6. r on vs. supplies, v dd = 12 v 10% 90 80 70 60 50 40 30 0 5.04.54.03.53.02.52.01.51.00.5 source voltage (v) r on ( ?) 05464-025 v dd = 8v v dd = 7.2v v dd = 8.8v t a = 25c i ds = 10ma figure 7. r on vs. source voltage, v dd = 8 v 10% 80 70 60 50 40 30 20 10 0 ?5 1 0 ?1 ?2 ?3 ?4 source voltage (v) r on ( ?) 05464-026 v dd = +5v v ss = ?5v i ds = 10ma t a = +85c t a = +125c t a = +25c t a = ?40c figure 8. r on vs. temperature, dual 5 v supplies 60 50 40 30 20 10 0 0 6 5 4 3 2 1 source voltage (v) r on ( ?) 05464-027 t a = +125c t a = +85c t a = +25c t a = ?40c v dd = 12v v ss = 0v i ds = 10ma figure 9. r on vs. temperature, v dd = 12 v
adg2128 data sheet rev. d | page 12 of 28 80 70 60 50 40 30 20 10 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 source voltage (v) r on ( ?) 05464-013 t a = +125c t a = +85c t a = +25c t a = ?40c v dd = 8v v ss = 0v i ds = 10ma figure 10 . r on vs. temperature, v dd = 8 v 16 14 12 10 8 6 4 2 0 0 20 40 60 80 100 120 temperature (c) leakage currents (na) 05464-014 x channels, v bias = +4v y channels, v bias = ?2v v dd = +5v v ss = ?5v figure 11 . on leakage vs. temperature, dual 5 v supplies 12 10 8 6 4 2 0 ?2 0 20 40 60 80 100 120 temperature (c) leakage currents (na) 05464-015 x, y channels; v bias = ?2v on x channel; +4v on y channel x, y channels; v bias = +4v on x channel; ?2v on y channel v dd = 5v v ss = ?5v figure 12 . off leakage vs. temperature, dual 5 v supplies 18 12 16 14 10 8 6 4 2 0 ?2 0 20 40 60 80 100 120 temperature (c) leakage currents (na) 05464-011 y channels, v bias = 7v x channels, v bias = 7v y channels, v bias = 1v v dd = 12v v ss = 0v figure 13 . on leakage vs. temperature, 12 v single supply 9 6 8 7 5 4 3 2 1 0 ?1 0 20 40 60 80 100 120 temperature (c) leakage currents (na) 05464-012 x, y channels; v bias = 7v on x channel; 1v on y channel x, y channels; v bias = 1v on x channel; 7v on y channel v dd = 12v v ss = 0v figure 14 . off leakage vs . temperature, 12 v single supply 0 ?5 .0 supply vo lt age (v) charge injection (pc) 05464-030 ?0 .5 ?1 .0 ?1 .5 ?2 .0 ?2 .5 ?3 .0 ?3 .5 ?4 .0 ?4 .5 ?3?5 ?1 1 3 5 7 9 11 v dd = +5v, v ss = ?5v v dd = + 12 v, v ss = 0v figure 15 . charge injection vs. supply voltage
data sheet adg2128 rev. d | page 13 of 28 tempe ra t ur e (c) t on /t off (ns) 05464-029 100 120 140 160 180 200 220 240 ?40 ?2 0 0 2 0 40 60 80 100 120 t on t off v dd = 12 v, v ss = 0v v dd = 5v, v ss = 0v figure 16 . t on /t off times vs. temperature ?2 ?8 ?7 ?6 ?5 ?4 ?3 10 1g 10g 10m 100k 1k frequency (hz) insertion loss (db) 05464-020 v dd = +5v v ss = ?5v t a = 25c figure 17 . individual inputs to individual outputs bandwidth , dual 5 v supply ?1 ?2 ?8 ?7 ?6 ?5 ?4 ?3 10 1g 10g 10m 100k 1k frequency (hz) insertion loss (db) 05464-021 v dd = 12v v ss = 0v t a = 25c figure 18 . individual inputs to individual outputs bandwidth , 12 v single supply 0 ?1 ?2 ?8 ?7 ?6 ?5 ?4 ?3 frequency (hz) insertion loss (db) 05464-022 10 1g 10g 10m 100k 1k v dd = +5v v ss = ?5v t a = 25c figure 19 . one input to eight outputs bandwidth, 5 v dual supply ?10 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 10 1g 10m 100k 1k frequency (hz) insertion loss (db) 05464-023 v dd = +5v to +12v v ss = ?5v to 0v t a = 25c figure 20 . off isolation vs. frequenc y ?120 ?100 ?80 ?60 ?40 ?20 10 1g 10m 100k 1k frequency (hz) insertion loss (db) 05464-024 v dd = +5v to +12v v ss = ?5v to 0v t a = 25c adjacent channels non-adjacent channels figure 21 . crosstalk vs. frequency
adg2128 data sheet rev. d | page 14 of 28 0.35 0.05 0.30 0.25 0.20 0.15 0.10 0 0 0.5 1.0 1.5 2.0 2.5 3.0 v l = 5v v l = 3v frequency (mhz) i l (ma) 05464-016 v dd = +5v v ss = ?5v figure 22 . digital current ( i l ) vs. frequency 1.8 0.4 0.6 0.8 1.0 1.2 1.4 1.6 0.2 0 0 6 5 4 3 2 1 v logic (v) i l (ma) 05464-019 v l = 5v v l = 3v figure 23 . digital current (i l ) vs. v logic for varying digital supply voltage 0 ?120 100 1g frequency (hz) acpsrr (db) ?20 ?40 ?60 ?80 ?100 1k 10k 100k 1m 10m 100m 05464-028 v dd = 5v/12v v ss = ?5v/0v t a = 25c 0.2v p-p ripple switch off, without decoupling switch on, without decoupling with decoupling figure 24 . acpsrr
data sheet adg2128 rev. d | page 15 of 28 test circuits the test c ircuits show measurements on one channel for clarity, but the circuit applies to any of the switches in the matrix . 05464-031 x y v s r on = v1/i ds i ds v1 figure 25 . o n resistance 05464-032 x y v x v y i off a a i off figure 26 . off leakage 05464-033 x y v y nc i on a figure 27 . on leakage 05464-034 v x x y v out 50% 90% 9th d at a bit gnd 0. 1f 0. 1f v ss v out v dd v ss v dd c l 35p f r l 300 ? t off and t on figure 28 . switching times, t on , t off 05464-035 xy v x c l 1n f r x q inj = c l v out v out gnd 0.1 f 0.1 f v ss v ss v dd v dd v out sw on d at a bit v out sw off figure 29 . charge injection 05464-036 v x 50? r l 50 ? v x y 0. 1f v s v out off isol a tion = 20 log network ana lyzer 0. 1f v ss v ss 50 ? v dd v dd v out gnd figure 30 . off isolation 05464-037 v x 50? r l 50 ? v x y 0. 1f v out without switch v out with switch insertion loss = 20 log network ana lyzer 0. 1f v ss v ss v dd v dd v out gnd figure 31 . bandwidth
adg2128 data sheet rev. d | page 16 of 28 05464-038 y1 y2 x2 v x v ou t network ana lyzer d at a bit v out r 50? r l 50? 50? r 50? x1 channel- t o-channe l cross t alk = 20 log gnd v s 0.1f 0.1f v dd v dd v ss v ss figure 32 . channel -to- channel crosstalk
data sheet adg2128 rev. d | page 17 of 28 terminology on resistance ( r on ) the series on - channel resistance measured between the x input/ou tput and the y input/output. on resistance match ( ?r on ) the channel - to - channel matching of o n resistance when channels are operated under identical conditions. on resistance flatness ( r flat (on) ) the variation of o n resistance over the specified range produ ced by the specified analog input voltage change with a constant load current. channel off leakage (i off ) the s um of leakage currents into or out of an o ff channel input. channel on leakage (i on ) the c urrent loss/g ain through an o n- channel resistance, cr eating a voltage offset across the device. input leakage current (i in ) the current flowing into a digital input when a specified low level or high level voltage is applied to that input. input off capacitan ce (c off ) the capacitance between an analog inpu t and ground when the switch channel is off. input/output on capacitance (c on ) the capacitance between the inputs or outputs and ground when the switch channel is on. digital input capacitance (c in ) the capacitan ce between a digital input and g round. ou tput on switching time (t on ) the time required for the switch channel to close. the time is measured from 50% of the logic input change to the time the output reaches 10% of the final value. output off switching time (t off ) the time required for the switc h to open. this time is measured from 50% of the logic input change to the time the output reaches 90% of the switch off condition. total harmonic distortion + noise ( thd + n ) the ratio of the harmonic amplitudes plus noise of a signal to the fundamental. ?3 db bandwidth the f requency at which the output is attenuated by 3 db. off isolation the m easure of unwanted signal coupling through an off switch. crosstalk the m easure of unwanted signal that is coupled through from one channel to another as a result of parasitic capacitance. differential gain the measure of how much color saturation shift occurs when the lu minance level changes. both attenuation and amplification can occur; therefore , the largest amplitude change betw een any two levels is specified an d is expressed as a percentage of the largest chrominance amplitude. differential phase the measure of how much hue shift occurs whe n the luminance level changes. it c an be a negative or positive value and is expressed in degrees of sub carrier phase. cha rge injection the m easure of the glitch impulse transferred from the digital input to the analog output during o n/ off switching. input high voltage (v inh ) the minimum input voltage for logic 1. input low voltage (v inl ) the m aximum input voltage for logic 0 . output low voltage (v ol ) the minimum input voltage for logic 1. input low voltage (v inl ) t he m aximum output voltage for logic 0. i dd positive supply current. i ss negative supply current.
adg2128 data sheet rev. d | page 18 of 28 theory of operation the adg2128 is an analog cross point switch w ith an array size of 8 12. the 12 rows are referred to as the x input/output lines , while the eight columns are referred to as the y input/output lines. the device i s fully flexible in that it connect s any x line or number of x lin es with any y line when turned o n. similarly, it connect s any x line with any number of y lines when turned o n. control of the adg2128 is carried out via an i 2 c interface. the device can be operated from single supplies of up to 13.2 v or from dual 5 v supplies. the adg2128 has many attractive features, such as the ability to reset all the switches, the ability to update many switches at the same time , and the option of reading back the status of any switch. all of these features are described in more detail here in the theory of operation section. reset /power - on reset the adg 2128 offers the ability to r eset all of the 96 switches to the off s tate. this is done through the reset pin. when the reset pin is low , all switches are open (o ff), and appropriate registers are cleared. note that the adg 2128 also has a power - on reset block. this ensures that all switches are in the o ff condition on power - up of the device. in addition , all interna l registers ar e filled with 0 s and remain so until a valid write to the adg2128 takes place. load switch (ldsw) ldsw is an active high command that allows a number of switches to be simultaneously updated. this is useful in applications where it is important to have s ynchronous transmission of signals. there are two ldsw modes: the transparent mode and the latched mode. transparent mode in this mode, the switch position change s after the new word is written in. ldsw is set to 1. latched mode in this mode , the switch positions are not updated at the same time that the input registers are written to. this is achieved by setting ldsw to 0 for each word (apart from the last word) written to th e device. then , setting ldsw to 1 for the last word allows all of the switches i n that sequence to be simultaneously updated . readback readback of the switch array conditions is also offered when in standard mode and f ast mode . readback enables the user to check the status of the switches of the adg2128 . this is very useful when debug ging a system.
data sheet adg2128 rev. d | page 19 of 28 serial interface the adg2128 is controlled via an i 2 c- compatible serial bus. the parts are connected to this bus as a slave device (no clock is generated by the switch). high speed i 2 c i nter face in addition to standard and full speed i 2 c , the adg2188 also supports the high speed (3.4 mhz) i 2 c interface. only the - hs models provide this added performance. see the ordering guide for details. serial bus address the adg2128 has a 7 - bit slave address. the four msbs ar e hard coded to 1110 , and the three lsbs ar e determined by the state of pin a0, pin a1 , and pin a2 . by offering the facility to hardware configure pin a0, pin a1 , and pin a2, up to eight of these devices can be connected to a single serial bus. the 2 - wire serial bus protocol operates as follows: 1. the master initiates data transfer by es tablishing a start condition , defined as when a high - to - low transition on the sda line occurs while scl is high. this indicates that an address/data stream follows. all slave peripherals conn ected to the serial bus respond to the start condition and shift in the next eight bits, consisting of a 7 - bit address (msb first) plus an r/ w bit that determines the direction of the data transfer, that is, whether data is written to or read from the slave device. 2. the peripheral whose address corresponds to the trans - mitted address responds by pulling t he sda line low during the ninth clock pulse, known as the a cknowledge bit. at this stage, all other devices on the bus remain idle while the selected device waits for data to be written to or read from its serial register. if the r/ w bit is 1 (high), the master reads from the slave device. if the r/ w bit is 0 (low), the master write s to the slave device. 3. data is transmitted over the serial bus in sequences of nine clock pulses: eight data bits followed by an a cknowl - edge bit from the receiver of the data. transitions on the sda line must occur during the low period of the clock signal, s cl, and remain stable during the high period of scl, because a low - to - high transition when the clock is high can be interpreted as a stop sig nal . 4. when all data bits h ave been read or written, a stop condition is established by the master. a stop condition is defined as a low - to - high transition on the sda line while scl is high. in w rite mode, the master pulls the sda line high during the 10th clock pulse to establish a stop condition . in r ead mode, the master issue s a no a cknowled ge for the nin th clock pul se (that is, the sda lin e remains high). the master then bring s the sda line low before the 10th clock pulse and then high during the 10th clock pulse to establish a stop condition. refer to figure 33 and figure 34 for a graphical explanation of the serial data transfer protocol.
adg2128 data sheet rev. d | page 20 of 28 writing to the adg21 28 input shift register the input shift register is 24 bits wide. a 3 - byte write is necessary when writing to this reg ister and is done under the cont rol of the serial clock i nput, scl. the contents of the three bytes of the input shift register are shown in figure 33 and described in table 6 . 05464-004 x x x x x x x ldsw db 0 (lsb) db 7 (msb) da ta bits da ta ax3 ax2 ax1 ax0 ay2 ay1 a y0 db 8 (lsb) db15 (msb) da ta bits 1 1 1 0 a2 a 1 a0 r /w db16 (lsb) device addr ess db23 (msb) figure 33 . data - words tale 6 . input shift register bit function descriptions bit mnemonic description db23 to db17 1110xxx the msbs of the adg2128 are set to 1110. the lsbs of the address byte are set by the state of the three address pins, pin a0, pin a 1 , and pin a2. db16 r/ w controls whether the adg2128 slave device is read from or written to. if r/ w = 1, the adg2128 is being r ead from. if r/ w = 0, t he adg2128 is being written to . db 15 data cont rols wh ether the switch is to be open (o ff ) or closed (on). if d ata = 0 , the switch is open/o ff . if d ata = 1, the switch is closed/o n. db14 to db11 a x3 to ax0 control s i/os x0 to x11. see table 7 for the decode truth t able . db 10 to db8 ay2 to ay0 control s i/os y0 to y7. see table 7 for the decode truth t able . db7 to db1 x dont care. db0 ldsw this bit is useful when a number of switches need to be simultaneously updated. if ldsw = 1, the switch p osition chan ge s after the new word is read . if ldsw = 0, t he input data is latched, but the switch position is not changed. as shown in table 6 , bit db11 to bit db14 con trol the x input/output lines, while bit db8 to bit db10 control the y input/output lines. table 7 show s the truth table for these bits. note the full coding sequence is written out for channel y0, and channel y1 to channel y7 follow a similar pattern. note also that the reset pin must be high when writing to the device. table 7 . address decode truth table db15 db14 db13 db12 db11 db10 db9 db8 switch configuration data ax3 ax2 ax1 ax0 ay2 ay1 ay0 1 0 0 0 0 0 0 0 x0 to y0 (o n) 0 0 0 0 0 0 0 0 x0 to y0 (o ff ) 1 0 0 0 1 0 0 0 x1 to y0 (o n) 0 0 0 0 1 0 0 0 x1 to y0 (o ff ) 1 0 0 1 0 0 0 0 x2 to y0 (o n) 0 0 0 1 0 0 0 0 x2 to y0 (o ff ) 1 0 0 1 1 0 0 0 x3 to y0 (o n) 0 0 0 1 1 0 0 0 x3 to y0 (o ff ) 1 0 1 0 0 0 0 0 x4 to y0 (o n) 0 0 1 0 0 0 0 0 x4 to y0 (o ff ) 1 0 1 0 1 0 0 0 x5 to y0 (o n) 0 0 1 0 1 0 0 0 x5 to y0 (o ff ) x 0 1 1 0 0 0 0 reserved x 0 1 1 1 0 0 0 reserved 1 1 0 0 0 0 0 0 x6 to y0 (o n) 0 1 0 0 0 0 0 0 x6 to y0 ( o ff ) 1 1 0 0 1 0 0 0 x7 to y0 (o n) 0 1 0 0 1 0 0 0 x7 to y0 (o ff ) 1 1 0 1 0 0 0 0 x8 to y0 (o n) 0 1 0 1 0 0 0 0 x8 to y0 (o ff )
data sheet adg2128 rev. d | page 21 of 28 db15 db14 db13 db12 db11 db10 db9 db8 switch configuration data ax3 ax2 ax1 ax0 ay2 ay1 ay0 1 1 0 1 1 0 0 0 x9 to y0 (o n) 0 1 0 1 1 0 0 0 x9 to y0 (o ff ) 1 1 1 0 0 0 0 0 x10 to y0 (o n) 0 1 1 0 0 0 0 0 x10 to y0 (o ff ) 1 1 1 0 1 0 0 0 x11 to y0 (o n) 0 1 1 0 1 0 0 0 x11 to y0 (o ff ) x 1 1 1 0 0 0 0 reserved x 1 1 1 1 0 0 0 reserved 1 0 0 0 0 0 0 1 x0 to y1 (o n) 0 0 0 0 0 0 0 1 x0 to y1 (o ff ) .. .. .. .. .. .. .. 1 1 1 0 1 0 0 1 x11 to y1 (o n) 1 0 0 0 0 0 1 0 x0 to y2 (o n) 0 0 0 0 0 0 1 0 x0 to y2 (o ff ) .. .. .. .. .. .. .. .. 1 1 1 0 1 0 1 0 x11 to y2 (o n) 1 0 0 0 0 0 1 1 x0 to y3 (o n) 0 0 0 0 0 0 1 1 x0 to y3 (o ff ) .. .. .. .. .. .. .. .. 1 1 1 0 1 0 1 1 x11 to y3 (o n) 1 0 0 0 0 1 0 0 x0 to y4 (o n) 0 0 0 0 0 1 0 0 x0 to y4 (o ff ) .. .. .. .. .. .. .. .. 1 1 1 0 1 1 0 0 x11 to y4 (o n) 1 0 0 0 0 1 0 1 x0 to y5 (o n) 0 0 0 0 0 1 0 1 x0 to y5 (o ff ) .. .. .. .. .. .. .. .. 1 1 1 0 1 1 0 1 x11 to y5 (o n) 1 0 0 0 0 1 1 0 x0 to y6 (o n) 0 0 0 0 0 1 1 0 x0 to y6 (o ff ) .. .. .. .. .. .. .. .. 1 1 1 0 1 1 1 0 x11 to y6 (o n) 1 0 0 0 0 1 1 1 x0 to y7 ( o n) 0 0 0 0 0 1 1 1 x0 to y7 (o ff ) .. .. .. .. .. .. .. .. 1 1 1 0 1 1 1 1 x11 to y7 (o n)
adg2128 data sheet rev. d | page 22 of 28 write operation when writing to the adg2128, the user must begin with an address byte and r/ w bit, after which the switch a cknowledge s that it is prepared to receive data by pulling sda low. this address byte is followed by the two 8 - bit words. the write operations for the switch array are shown in figure 34 . note that it is only the condition of the switch corresponding to the bits in the d ata bytes that change s state. all other switches retain their previous condition. read operation readback on the adg2128 has been desig ned to work as a tool for debug and can be used to output the status of any of the 96 switches of the device. the readba ck function is a 2 - step sequence that works as follows: 1. select the relevant x line that you wish to read back from. note that there are eight switches connecting that x line to the eight y lines. the next step involves writing to the ad g2128 to tell the p art that you would like to know the status of those eight switches . a. enter the i 2 c address of the adg2128, and set the r/ w bit to 0 to indicate that you are writing to the device. b. enter the r eadback address for the x line of interest, the addresses of which are shown in table 8 . note that the adg2 128 is expecting a 2 - byte write; therefore , be sure to enter another byte of dont cares . (see figure 35 ). c. the adg2128 t hen places the statu s of those eight switches in a register that can be read back. 2. the second step involves reading back from the register that holds the status of the eight switches associated with you r x line of choice. a. as before, enter the i 2 c address of the adg2128. thi s time , set the r/ w bit to 1 to indicate that you would like to read back from the device. b. as with a write to the device, the adg2128 outp uts a 2- byte sequence during r eadback . therefore , the first eight bits of data out that are read back are all 0s. the next eight bits of data that come back are the status of the eight y lines attached to that particular x line. if th e bit is a 1, then the switch is closed (on); similarly , if it is a 0, the switch is open (o ff). the entire read sequence is shown in figure 35 . 05464-005 data ax3 ax2 ax1 ax0 ay2 ay1 ay0 a0 r/w a1a2 x x x x x x x scl sda data byte data byte ack by switch stop cond by master start cond by master address byte ack by switch ack by switch ldsw figure 34 . write operation table 8 . readback addresses for each x l ine x l ine rb7 rb6 rb5 rb4 rb3 rb2 rb1 rb0 x0 0 0 1 1 0 1 0 0 x1 0 0 1 1 1 1 0 0 x2 0 1 1 1 0 1 0 0 x3 0 1 1 1 1 1 0 0 x4 0 0 1 1 0 1 0 1 x5 0 0 1 1 1 1 0 1 x6 0 1 1 1 0 1 0 1 x7 0 1 1 1 1 1 0 1 x8 0 0 1 1 0 1 1 0 x9 0 0 1 1 1 1 1 0 x10 0 1 1 1 0 1 1 0 x11 0 1 1 1 1 1 1 0
data sheet adg2128 rev. d | page 23 of 28 05464-006 dummy readback byte ack by switch stop cond by master readback byte start cond by master address byte ack by master no ack by master rb7 rb6 rb5 rb4 rb3 rb2 rb1 rb0 a0 r/w a1a2 x x x x x x x x scl sda a0 r/w a1 a2 y7 y6 y5 y4 y3 y2 y1 y0 scl sda data byte data byte ack by switch stop cond by master start cond by master address byte ack by switch no ack by switch figure 35 . read o peration
adg2128 data sheet rev. d | page 24 of 28 evaluation board the adg2128 evaluation board allows designers to evaluate the high performance adg2128 8 12 switch array with minimum effort. the evaluation kit includes a populated, tested adg2128 printed circuit board. the evaluation board i nterfaces to the usb port of a pc , o r it can be used as a stand alone evaluation board. software is available with the evaluation board that allows the user to easily program the adg2128 through the usb port . s chematic s of the evaluation board are shown in figure 36 and figure 37 . the software run s on any pc that has microsoft ? windows ? 2000 or windows xp installed. using the adg2128 ev aluation board the adg2128 evaluation kit is a test system designed to simplify the evaluation of the adg2128. each input/output of the part comes with a socket specifically chosen for easy audio/video evaluation. an application note is also available with the evaluation board and gives full information on operating the e valuation board. power supply the adg2128 evaluation board can be operated with both single and dual s upplies. v dd and v ss are supplie d externally by the user. the v l supply can be applied externally , or the usb port can be used to power the digital circui tr y.
data sheet adg2128 rev. d | page 25 of 28 schematics 3.3v r6 75 c9 0.1uf c10 22pf c17 22pf r10 10k r5 75 r7 0r c18 0.1uf c5 0.1uf c6 0.1uf c7 0.1uf c8 0.1uf c19 0.1uf c20 0.1uf c21 0.1uf c22 0.1uf 1 a0 2 a1 3 a2 4 vss 5 sda 6 scl 7 wp 8 vcc u2 24lc64 50 pd5/fd13 51 pd6/fd14 52 pd7/fd15 54 clkout 1 rdy0/*slrd 2 rdy1/*slwr 4 xtalout 5 xtalin 8 d+ 9 d- 13 ifclk 14 rsvd 15 scl 16 sda 18 pb0/fd0 19 pb1/fd1 20 pb2/fd2 21 pb3/fd3 49 pd4/fd12 48 pd3/fd11 47 pd2/fd10 46 pd1/fd9 45 pd0/fd8 44 *wakeup 42 reset 40 pa7/*fld/slcs 39 pa6/*pktend 38 pa5/fifoadr1 37 pa4/fifoadr0 36 pa3/*wu2 35 pa2/*sloe 34 pa1/int1 33 pa0/int0 31 ctl2/*flagc 30 ctl1/*flagb 29 ctl0/*flaga 25 pb7/fd7 24 pb6/fd6 23 pb5/fd5 22 pb4/fd4 3 avcc 7 vcc 11 vcc 17 vcc 27 vcc 32 vcc 43 vcc 55 vcc 6 agnd 10 gnd 12 gnd 26 gnd 28 gnd 41 gnd 53 gnd 56 gnd u3 cy7c68013-csp c4 10uf c23 2.2uf 1 vbus 2 d- 3 d+ 4 io 5 gnd shield j1 usb-mini-b xtal1 24 mhz r11 1k d4 8 in1 7 in2 5 sd 4 gnd 1 out1 2 out2 6 error 3 nr u5 adp3303-3.3 c15 0.1uf c16 0.1uf t1 t2 t3 c3 0.1uf c13 10uf c14 10uf +3.3v +3.3v +3.3v +3.3v +3.3v +3.3v sda scl +3.3v dgnd 5vusb +3.3v 05464-039 figure 36 . eval - adg2128 eb schematic, usb controller s ection
adg2128 data sheet rev. d | page 26 of 28 05464-040 1 vss 2 nc 3 x0 4 x1 5 x2 6 x3 7 x4 8 x5 9 y0 10 y1 11 y2 12 y3 13 y4 14 y5 15 y6 16 y7 17 x6 18 x7 19 x8 20 x9 21 x10 22 x11 23 nc 24 vdd 25 vl 26 sda 27 scl 28 a0 29 a1 30 a2 31 reset 32 gnd u1 adg2128ycp t4 t5 r1 r2 r3 r4 r12 r13 r14 r15 r16 r17 r18 r19 r20 r21 r22 r23 r24 r25 r26 r27 reset k3 k1 k2 d1 k5 r28 10k r29 10k r30 10k r31 10k scl sda c11 0.1uf + c12 10uf 6v3 c24 0.1uf + c25 10uf 6v3 c28 0.1uf + c29 10uf 16v c1 0.1uf c26 0.1uf c30 0.1uf j2-2 j2-3 j2-4 j2-1 + c2 16v 10uf + c27 6v3 10uf + c31 6v3 10uf r8 2k2 r9 2k2 b a k4 1 3 x0_x1-a 2 4 x0_x1-b 1 3 x2_x3-a 2 4 x2_x3-b 1 3 x4_x5-a 2 4 x4_x5-b 1 3 y0_y1-a 2 4 y0_y1-b 1 3 y2_y3-a 2 4 y2_y3-b 1 3 y4_y5-a 2 4 y4_y5-b 1 3 y6_y7-a 2 4 y6_y7-b 1 3 x6_x7-a 2 4 x6_x7-b 1 3 x8_x9-a 2 4 x8_x9-b 1 3 x10_x11-a 2 4 x10_x11-b scl sda agnd avss avdd dgnd agnd avdd 5vusb vl dgnd agnd avss vl avdd vl avss avdd agnd +3.3v vss figure 37 . eval - adg2128 eb s chematic, chip s ection
data sheet adg2128 rev. d | page 27 of 28 outline dimensions compliant to jedec standards mo-220-whhd. 112408-a 1 0.50 bsc bot t om view top view pin 1 indic at or 32 9 16 17 24 25 8 exposed pa d pin 1 indic at or 3.25 3.10 sq 2.95 sea ting plane 0.05 max 0.02 nom 0.20 ref coplanarity 0.08 0.30 0.25 0.18 5.10 5.00 sq 4.90 0.80 0.75 0.70 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 0.50 0.40 0.30 0.25 min figure 38 . 32 - lead lead frame chip scale package [lfcsp _w q] 5 mm x 5 mm body, very very t hin quad (cp - 32 -7) dimensions shown in millimeters ordering guide model 1 , 2 temperature range i 2 c speed package description package option adg2128bcpz - reel ?40c to +85c 100 khz, 400 khz 32- lead lead frame chip scale package [lfcsp_ w q] cp -32 -7 adg2128bcpz - reel7 ?40c to +85c 100 khz, 400 khz 32 - lead lead frame chip scale package [lfcsp_ w q] cp - 32 - 7 adg2128bcpz -hs -rl 7 C 40c to +85 c 100 khz, 400 khz, 3.4 mh z 32- lead lead frame chip scale package [lfcsp_ w q] cp -32 -7 adg2128wbcpz - reel7 ?40c to +8 5c 100 khz, 400 khz 32- lead lead frame chip scale package [lfcsp_ w q] cp -32 -7 adg2128ycpz - reel ?40c to +125c 100 khz, 400 khz 32- lead lead frame chip scale package [lfcsp_ w q] cp -32 -7 adg2128ycpz - reel7 ?40c to +125c 100 khz, 400 khz 32- lead lead frame chip scale package [lfcsp_ w q] cp -32 -7 adg2128 ycp z- hs -rl 7 C 40c to +125c 100 khz, 400 khz, 3.4 mhz 32- lead lead f rame chip scale package [lfcsp_w q] cp -32 -7 eval -ad g2128eb z evaluation board 1 z = rohs compliant part . 2 w = qualified for automotive applications. automotive products the adg2128w models are available with controlled manufacturing to support the quality and reliability requirements of automo tive applications. note that these automotive models may have specifications th at differ from the commercial models; therefore, designers should review the specifications section of this data sheet carefully. only the automotive grade products shown are available for use in automotive applica tions. contact your local analog devices account representative for specific product ordering information and to obtain the specific automotive reliability reports for these models.
adg2128 data sheet rev. d | page 28 of 28 notes purchase of licensed i 2 c components of analog devices or one of its sublicensed associated companies conveys a license for the purchaser under the philips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. ? 2006 C 2012 analog devices, inc. a ll rights reserved. trademarks and registered trademarks are the property of their respective owners. d05464 -0- 10 /12(d)


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